Ducky's EDA Experience
Electronic Design Automation consultant since 4/90, specializing in MOTIVE:
- Wrote and augmented numerous C, awk, make, perl, and csh programs to
improve usability of Ikos, Synopsis, and MOTIVE, including software to
present simpler user interfaces, translate between vendor formats,
queue jobs, and improve readability of output.
- Analyzed timing using MOTIVE for chips and boards
for a variety of clients, including Nexgen Microsystems, Cray
Research, Amdahl, Unisys, SGI, Apple, Data General, AMD, and Sun.
- Analyses have required creative manipulation of MOTIVE to deal properly with
precharged buses, false paths, and unusual clocking schemes.
- Performed cross-talk and transmission line analysis on three boards
using TLC and XNS.
- Reduced Ikos primitive count for extremely large design by 40% by
optimizing macros and library elements. Developed approximately 200
At Arix Corp (my last permanent position):
- Wrote Cadnetix to Verilog netlist translator (in C).
- Simulated dual-processor 68040 board with 400 ICs using Verilog with
Logic Automation models. Wrote behavioral models for memory board,
arbiter, and several glue parts.